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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9214 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 10-bit, 65/80/105 msps 3 v a/d converter functional block diagram ref timing 10 10 agnd ad9214 av dd drv dd pwrdwn or d 9 ? 0 dgnd encode a in a in dfs/gain refsense ref pipeline adc core t/h buffer output register features snr = 57 db @ 39 mhz analog input (C0.5 dbfs) low power 190 mw at 65 msps 285 mw at 105 msps 30 mw power-down mode 300 mhz analog bandwidth on-chip reference and track/hold 1 v p-p or 2 v p-p analog input range option single 3.3 v supply operation (2.7 vC3.6 v) twos complement or offset binary data format option applications battery-powered instruments hand-held scopemeters low-cost digital oscilloscopes ultrasound equipment cable reverse path broadband wireless residential power line networks product description the ad9214 is a 10-bit monolithic sampling analog-to- digital converter (adc) with an on-chip track-and-hold circuit, and is optimized for low cost, low power, small size, and ease of use. the product operates up to 105 msps conversion rate with outstanding dynamic performance over its full operating range. the adc requires only a single 3.3 v (2.7 v to 3.6 v) power supply and an encode clock for full performance operation. no external reference or driver components are required for many applica tions. the digital outputs are ttl/cmos com patible and a separate output power supply pin supports in terfacing with 3.3 v or 2.5 v logic. the clock input is ttl/cmos compatible. in the power-down state, the power is reduced to 30 mw. a gain option allows support for either 1 v p-p or 2 v p-p analog signal input swing. fabricated on an advanced cmos process, the ad9214 is available in a 28-lead surface-mount plastic package (28-ssop) specified over the industrial temperature range (?0 c to +85 c). product highlights high performance?utstanding ac performance from 65 msps to 105 msps. snr greater than 55 db typical and as high as 58 db. low power?he ad9214 at 285 mw consumes a fraction of the power available in existing high-speed monolithic solutions. in sleep mode, power is reduced to 30 mw. single supply?he ad9214 uses a single 3 v supply, simplify- ing system power supply design. it also features a separate digital output driver supply line to accommodate 2.5 v logic families. small package?he ad9214 is packaged in a small 28-lead surface-mount plastic package (28-ssop).
rev. d C2C ad9214?pecifications dc specifications test ad9214-65 ad9214-80 ad9214-105 parameter temp level min typ max min typ max min typ max unit resolution 10 10 10 bits accuracy no missing codes 25 c vi guaranteed guaranteed guaranteed full vi guaranteed guaranteed offset error full vi ?8 0 +18 ?8 0 +18 ?8 0 +18 lsb gain error 1 25 c i ? +8 ? +8 ? +8 % fs differential nonlinearity 2 25 c i ?.0 0.5 +1.0 ?.0 0.5 +1.2 ?.0 0.8 +1.5 lsb (dnl) full v ?.0 +1.2 ?.0 +1.4 +1.7 lsb integral nonlinearity 2 25 c i ?.35 0.75 +1.35 ?.5 0.75 +1.5 ?.2 1.5 +2.2 lsb (inl) full v ?.9 +1.9 ?.8 +1.8 ?.5 +2.5 lsb temperature drift offset error full v 16 16 16 ppm/ c gain error 1 full v 150 150 150 ppm/ c reference voltage full v 80 80 80 ppm/ c reference (ref) internal reference voltage 25 c vi 1.18 1.23 1.28 1.18 1.23 1.28 1.18 1.23 1.28 v output current 3 full v 200 200 200 a input current 4 full v 123 123 123 a input resistance full v 10 10 10 k ? analog inputs (a in , a in ) differential input range full v 1 or 2 1 or 2 1 or 2 v p-p common-mode voltage full v av dd /3 av dd /3 av dd /3 v differential input resistance 5 full v 20 20 20 k ? differential input capacitance full v 5 5 5 pf power supply supply voltages av dd full iv 2.7 3.6 2.7 3.6 2.7 3.6 v drv dd full iv 2.7 3.6 2.7 3.6 2.7 3.6 v supply current i avdd (av dd = 3.0 v) 6 full vi 64 75 90 105 95 110 ma power-down current 7 i avdd (av dd = 3.0 v) full vi 10 15 10 15 10 15 ma power consumption 8 full vi 190 220 250 300 285 325 mw psrr 25 ci 0.5 1 1 lsb/v full v 2 2 2 mv/v notes 1 gain error and gain temperature coefficient are based on the adc only (with a fixed 1.25 v external reference). 2 measured with 1 v a in range for ad9214-80 and ad9214-105. measured with 2 v a in range for ad9214-65. 3 refsense externally connected to agnd, ref is configured as an output for the internal reference voltage. 4 refsense externally connected to av dd , ref is configured as an input for an external reference voltage. 5 10 k ? to av dd /3 on each input. 6 i avdd is measured with an analog input of 10.3 mhz, 0.5 dbfs, sine wave, rated encode rate, and pwrdn = 0. see typical performance c haracteristics and applications section for i drvdd . 7 power-down supply currents measured with pwrdn = 1; rated encode rate, a in = full-scale dc input. 8 power consumption measured with a in = full-scale dc input. specifications subject to change without notice. (av dd = 3 v, drv dd = 3 v; t min = ?0 c, t max = +85 c; external 1.25 v voltage reference and rated encode frequency used, unless otherwise noted.)
rev. d C3C ad9214 digital specifications test ad9214-65 ad9214-80 ad9214-105 parameter temp level min typ max min typ max min typ max unit digital inputs 1 logic ??voltage full iv 2.0 2.0 2.0 v logic ??voltage full iv 0.8 0.8 0.8 v input capacitance full v 2.0 2.0 2.0 pf digital outputs 2 logic compatibility cmos/ttl cmos/ttl cmos/ttl v logic ??voltage full vi drv dd ?50 mv drv dd ?50 mv drv dd ?50 mv v logic ??voltage full vi 50 50 50 mv notes 1 digital inputs include encode and pwrdn. 2 digital outputs include d0?9 and or. specifications subject to change without notice. ac specifications 1 test ad9214-65 ad9214-80 ad9214-105 parameter temp level min typ max min typ max min typ max unit snr analog input 10 mhz 25 c i 55.5 58.3 56.0 58.1 51.0 53.0 db @ ?.5 dbfs 39 mhz 25 c i 57.1 55.0 57.1 50.5 53.0 db 51 mhz 25 c v 55.0 53.0 db 70 mhz 25 c v 54.0 52.6 db sinad analog input 10 mhz 25 c i 55.0 57.8 55.5 57.6 50.0 52.0 db @ ?.5 dbfs 39 mhz 25 c i 56.7 54.5 56.7 50.0 52.0 db 51 mhz 25 c v 54.5 52.0 db 70 mhz 25 c v 52.0 db effective number of bits analog input 10 mhz 25 c i 8.9 9.3 9.0 9.3 8.4 bit @ ?.5 dbfs 39 mhz 25 c i 9.2 8.8 9.2 8.4 bit 51 mhz 25 c v 8.8 8.4 bit 70 mhz 25 c v 8.5 8.4 bit second harmonic distortion analog input 10 mhz 25 c i ?6 ?9 ?4 74 ?2 ?8 dbc @ ?.5 dbfs 39 mhz 25 c i ?5 ?3 76 ?2 ?1 dbc 51 mhz 25 c v ?2 ?4 dbc 70 mhz 25 c v ?5 ?2 dbc third harmonic distortion analog input 10 mhz 25 c i ?3.5 ?1 ?3 72 ?9 ?4 dbc @ ?.5 dbfs 39 mhz 25 c i ?0 ?3 74 ?9 ?7 dbc 51 mhz 25 c v ?8 ?1 dbc 70 mhz 25 c v ?5 dbc sfdr analog input 10 mhz 25 c i 63.5 71 63 71 57 62 dbc @ ?.5 dbfs 39 mhz 25 c i 70 63 71 57 62 dbc 51 mhz 25 c v 67 62 dbc 70 mhz 25 c v 64 62 dbc two-tone intermod distortion 2 analog input @ ?.5 dbfs 25 c v 76 74 72 dbfs analog input bandwidth 25 c v 300 300 300 mhz notes 1 ac specifications based on a 1.0 v p-p full-scale input range for the ad9214-80 and ad9214-105, and a 2.0 v p-p full-scale inpu t range for the ad9214-65. an external reference is used. 2 f1 = 29.3 mhz, f2 = 30.3 mhz. specifications subject to change without notice. (av dd = 3 v, drv dd = 3 v; encode = maximum conversion rate; t min = ?0 c, t max = +85 c; external 1.25 v voltage reference used, unless otherwise noted.) (av dd = 3 v, drv dd = 3 v; t min = ?0 c, t max = +85 c)
rev. d C4C ad9214?pecifications switching specifications test ad9214-65 ad9214-80 ad9214-105 parameter temp level min typ max min typ max min typ max unit encode input parameters * maximum conversion rate full vi 65 80 105 msps minimum conversion rate full iv 20 20 20 msps encode pulsewidth high (t eh ) full iv 6.0 5.0 3.8 ns encode pulsewidth low (t el ) full iv 6.0 5.0 3.8 ns aperture delay (t a )25 c v 2.0 2.0 2.0 ns aperture uncertainty (jitter) 25 c v 3 3 3 ps rms data output parameters pipeline delays full iv 5 5 5 cl ock cycle output valid time (t v ) * full v 3.0 4.5 3.0 4.5 3.0 4.5 ns output propagation delay * (t pd ) full v 4.5 6.0 4.5 6.0 4.5 6.0 ns transient response time 25 cv555ns out-of-range recovery time 25 cv555ns * t v and t pd are measured from the 1.5 v level of the encode input to the 50% levels of the digital output swing. the digital output load d uring test is not to exceed an ac load of 5 pf or a dc current of 40 a. specifications subject to change without notice. a in encode d9 d0 sample n sample n+1 sample n+2 sample n+3 sample n+4 sample n+5 t a t eh t el 1/f s t pd t v data n 5 data n 4 data n 3 data n 2 data n 1 data n figure 1. timing diagram (av dd = 3 v, drv dd = 3 v; encode = maximum conversion rate; t min = ?0 c, t max = +85 c; external 1.25 v voltage reference used, unless otherwise noted.)
rev. d ad9214 C5C absolute maximum ratings 1 electrical av dd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v max drv dd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v max analog input voltage . . . . . . . . . . . ?.5 v to av dd + 0.5 v analog input current . . . . . . . . . . . . . . . . . . . . . . . 0.4 ma digital input voltage . . . . . . . . . . . ?.5 v to av dd + 0.5 v digital output current . . . . . . . . . . . . . . . . . . 20 ma max ref input voltage . . . . . . . . . . . . . ?.5 v to av dd + 0.5 v environmental 2 operating temperature range (ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c to +125 c maximum junction temperature . . . . . . . . . . . . . . . 150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . 150 c storage temperature range (am bient) . . . ?5 c to +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not n ecessarily implied. exposure to absolute maximum rating condi- tions for an e xtended period of time may affect device reliability. 2 typical thermal impedances (package = 28 ssop); ja = 49 c/w. these measurements were taken on a 6-layer board in still air with a solid ground plane. explanation of test levels i 100% production tested. ii 100% production tested at 25 c and guaranteed by design and characterization at specified temperatures. iii sample tested only iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25 c and guaranteed by design and characterization for industrial temperature range. ordering guide model temperature range package description package option ad9214brs-65 ?0 c to +85 c (ambient) 28-lead shrink small outline package rs-28 ad9214brs-80 ?0 c to +85 c (ambient) 28-lead shrink small outline package rs-28 AD9214BRS-105 ?0 c to +85 c (ambient) 28-lead shrink small outline package rs-28 ad9214-65pcb 25 c evaluation board with ad9214-65 ad9214-105pcb 25 c evaluation board with ad9214-105 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9214 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. d ad9214 C6C pin function descriptions pin no. mnemonic function 1 or cmos output; out-of-range indicator. logic high indicates the analog input voltage was outside the converter? range for the current output data. 2 dfs/gain data format select and gain mode select. connect externally to av dd for two? complement data format and 1 v p-p analog input range. connect externally to agnd for offset binary data format and 1 v p-p analog input range. connect externally to ref (pin 4) for two? complement data format and 2 v p-p analog input range. floating this pin will configure the device for offset binary data format and a 2 v p-p analog input range. 3 refsense reference mode select pin for the adc. this pin is normally connected externally to agnd, which enables the internal 1.25 v reference, and configures ref (pin 4) as an analog reference output pin. connecting refsense externally to av dd disables the internal reference, and config- ures ref (pin 4) as an external reference input. in this case, the user must drive ref with a clean and accurate 1.25 v ( 5%) reference input. 4 ref reference input or output as configured by refsense (pin 3). when conf igured as an output (refsense = agnd), the internal reference (nominally 1.25 v) is enabled and is available to the user on this pin. when configured as an input (refsense = av dd ), the user must drive ref with a clean and accurate 1.25 v ( 5%) reference. this pin should be bypassed to agnd with an external 0.1 f capacitor, whether it is configured as an input or output. 5, 8, 11 agnd analog ground 6, 7, 12 av dd analog power supply, nominally 3 v 9a in positive terminal of the differential analog input for the adc. 10 a in negative terminal of the differential analog input for the adc. this pin can be left open if oper ating in single-ended mode, but it is preferable to match the impedance seen at the positive terminal (see driving the analog inputs). 13 encode encode clock for the adc. the ad9214 samples the analog signal on the rising edge of encode. 14 pwrdn cmos-compatible power-down mode select, logic low for normal operation; logic high for power-down mode (digital outputs in high impedance state). pwrdn has an internal 10 k ? pull-down resistor to ground. 15, 23 dgnd digital output ground 16, 24 drv dd digital output driver power supply. nominally 2.5 v to 3.6 v. 17?2, 25?8 d0 (lsb)?5, cmos digital outputs of adc d6?9 (msb) pin configuration 28-lead shrink small outline package top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad9214 pwrdn encode av dd agnd a in a in agnd or dfs/gain refsense ref av dd av dd agnd dgnd drv dd d0 (lsb) d1 d2 d3 d4 d9 (msb) d8 d7 d6 d5 dgnd drv dd
rev. d ad9214 C7C terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input resistance, differential analog input capacitance and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capaci- tance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differen- tial voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. then the difference is computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits the effective number of bits (enob) is calculated from the measured snr based on the equation: enob sinad db full scale actual measured = + ? ? ? ? ? ? . log . 176 20 602 encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the en code pulse should be left in logic 1 state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. see timing implications of changing t ench in text. at a given clock rate, these specs define an acceptable encode duty cycle. full-scale input power expressed in dbm. computed using the following equation: power v z full scale full scale rms input = ? ? ? ? ? ? ? ? ? ? ? ? 10 0 001 2 log . gain error gain error is the difference between the measured and ideal full scale input voltage range of the adc. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. noise (for any range within the adc) vz fs snr signal noise dbm dbc dbfs = ?? 0 001 10 10 . where z is the input impedance, fs is the full-scale of the device for the frequency in question, snr is the value for the particular input level and signal is the signal level within the adc reported in db below full-scale. this value includes both thermal and quantization noise. power supply rejection ratio (psrr) the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 0.5 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 0.5 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered), or dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an intermodulation distortion product. may be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc.
rev. d ad9214 C8C transient response time transient response is defined as the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. 15k 30k 40 15k 30k 40 a in av dd a in figure 2. analog input stage 2.6k 2.6k 600 encode figure 3. encode inputs 40 dv dd dx figure 4. digital output stage equivalent circuits 10k v ref 10k ref av dd figure 5. ref configured as an output 10k ref av dd figure 6. ref configured as an input out-of-range recovery time out-of-range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
rev. d ad9214 C9C frequency mhz 0 db 52.5 100 50 0 90 80 70 60 40 30 20 10 encode: 105msps a in : 50.3mhz @ 0.5dbfs snr: 53.0db enob: 8.5 bits sfdr: 64dbfs tpc 1. fft: f s = 105 msps, f in = ~50.3 mhz; a in = C0.5 dbfs differential, 1 v p-p analog input range 0 40 100 50 0 90 80 70 60 40 30 20 10 encode: 80msps a in : 70.3mhz @ 0.5dbfs snr: 54.0db enob: 8.5 bits sfdr: 64dbfs frequency mhz db tpc 2. fft: f s = 80 msps, f in = 70 mhz; a in = C0.5 dbfs, 1 v p-p analog input range frequency mhz 0 db 52.5 100 50 0 90 80 70 60 40 30 20 10 encode: 105msps a in : 70.3mhz @ 0.5dbfs snr: 52.6db enob: 8.4 bits sfdr: 62.6dbfs tpc 3. f ft: f s = 105 msps; f in = 70 mhz (1 v p-p) typical performance characteristics frequency mhz 0 db 52.5 100 50 0 90 80 70 60 40 30 20 10 encode: 65msps a in : 15.3mhz @ 0.5dbfs snr: 56.9db enob: 9.2 bits sfdr: 70db tpc 4. fft: f s = 65 msps, f in = 15.3 mhz (2 v p-p) with ad8138 driving a in a in frequency mhz 0 db 70 50 100 40 60 70 80 90 60 50 40 30 20 10 3rd sfdr 2nd (1/)

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rev. d ad9214 C10C frequency mhz 0 db 70 40 80 90 100 60 40 20 60 50 80 3rd sfdr 2nd tpc 7. h armonic distortion (second and third) and sfdr vs. a in frequency (1 v p-p and 2 v p-p, f s = 65 msps) db 100 50 0 90 80 70 60 40 30 20 10 encode: 80msps a in : 29.3mhz @ 6dbfs 30.3mhz @ 6dbfs sfdr: 74dbfs frequency mhz 0 40 tpc 8. two-tone intermodulation distortion (29.3 mhz, 30.3 mhz; 1 v p-p, f s = 80 msps) db 100 50 0 90 80 70 60 40 30 20 10 frequency mhz 0 52.5 encode: 105msps a in : 30mhz @ 6dbfs 31mhz @ 6dbfs sfdr: 73dbfs tpc 9. two-tone intermodulation distortion (30 mhz and 31 mhz; 1 v p-p, f s = 105 msps) encode rate msps signal level db 80 45 75 40 55 60 65 70 60 40 20 50 sinad 2v p p sinad 1v p p sfdr 2v p p sfdr 1v p p 100 120 tpc 10. sinad and sfdr vs. encode rate (f in = 10.3 mhz; 1 v p-p and 2 v p-p) signal level db 45 75 55 60 65 70 50 pulsewidth high ns 246810 40 35 30 sinad 105msps sinad 80msps sfdr 105msps sfdr 80msps tpc 11. sinad and sfdr vs. encode pulsewidth high (1 v p-p) i avdd ma 40 120 80 100 60 encode rate msps 0 20 120 20 0 i avdd 4 12 8 10 6 2 0 i drvdd ma 40 60 80 100 i drvdd (1/'"
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rev. d ad9214 C11C temperature c 40 signal level db 46 58 44 48 50 52 54 80 40 0 56 sinad 10.3mhz/105msps snr 10.3mhz/105msps tpc 13. sinad/snr vs. temperature (f ain = 10.3 mhz, f encode = 105 msps, 1 v p-p) temperature c 40 % full scale 0.5 4.0 0.0 1.0 1.5 2.0 2.5 80 40 0 3.0 3.5 tpc 14. adc gain vs. temperature (with external 1.25 v reference) temperature c 40 reference voltage v 1.240 1.220 1.225 1.230 80 40 0 1.235 tpc 15. adc refe rence vs. temperature (with 200 a load) i ref a 500 v ref v 1.40 1.10 1.15 1.25 1.35 1.30 1.20 400 300 200 100 0 100 200 300 400 500 tpc 16. adc reference vs. current load code 0 inl lsb 1.00 1.00 0.75 0.00 0.75 0.25 0.25 128 256 384 512 640 768 896 1024 0.50 0.50 tpc 17. inl @ 80 msps code 0 dnl lsb 1.00 1.00 0.75 0.00 0.75 0.25 0.25 128 256 384 512 640 768 896 1024 0.50 0.50 tpc 18. dnl @ 80 msps
rev. d ad9214 C12C theory of operation the ad9214 architecture is a bit-per-stage pipeline converter utilizing switch capacitor techniques. these stages determine the 7 msbs and drive a 3-bit flash. each stage provides suffi- cient overlap and error correction allowing optimization of comparator accuracy. the input buffer is differential and both inputs are internally biased. this allows the most flexible use of ac or dc and differential or single-ended input modes. the out- put staging block aligns the data, carries out the error correction and feeds the data to output buffers. the output buffers are powered from a separate supply, allowing support of different logic families. during power-down, the outputs go to a high impedance state. applying the ad9214 encoding the ad9214 any high-speed a/d converter is extremely sensitive to the quality of the sampling clock provided by the user. a track/ hold circuit is essentially a mixer. any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the a/d output. for that reason, considerable care has been taken in the design of the encode input of the ad9214, and the user is advised to give commensurate thought to the clock source. the encode input is fully ttl/cmos compatible, and should normally be driven directly from a low jitter, crystal- controlled ttl/cmos oscillator. the encode input is internally biased, allowing the user to ac-couple in the clock signal. the cleanest clock source is often a crystal oscillator producing a pure sine wave. figure 7 illustrates ac coupling such a source to the encode input. encode low jitter crystal sine or pulse source 1v p-p ad9214 figure 7. ac-coupled encode circuit reference circuit the reference circuit of the ad9214 is configured by refsense (pin 3). by externally connecting refsense to agnd, the adc is configured to use the internal reference (~1.25 v), and the ref pin connection (pin 4) is configured as an output for the internal reference voltage. if refsense is externally connected to av dd , the adc is configured to use an external reference. in this mode, the ref pin is configured as a reference input, and must be driven by an external 1.25 v reference. in either configuration, the analog input voltage range (either 1 v p-p or 2 v p-p as determined by dfs/gain) will track the reference voltage linearly, and an external bypass capacitor should be connected between ref and agnd to reduce noise on the reference. in practice, no appreciable degradation in performance occurs when an external reference is adjusted 5%. dfs/gain the dfs/gain (data format select/gain) input (pin 2) controls both the output data format and gain (analog input volt- age range) of the adc. the table below describes its operation. table i. data format and gain configuration external differential dfs/gain analog input connection voltage range output data format agnd 1 v p-p offset binary av dd 1 v p-p two s complement ref 2 v p-p two s complement floating 2 v p-p offset binary driving the analog inputs the analog input to the ad9214 is a differential buffer. as shown in the equivalent circuits, each of the differential inputs is internally dc biased at ~av dd /3 to allow ac-coupling of the analog input signal. the analog signal may be dc-coupled as well. in this case, the dc load will be equivalent to ~10 k ? to av dd /3, and the dc common-mode level of the analog signals should be within the range of av dd /3 200 mv. for best dynamic performance, impedances at a in and a in should match. driving the analog input differentially optimizes ac performance, minimizing even order harmonics and taking advantage of common-mode rejection of noise. a differential signal may be transformer-coupled, as illustrated in figure 8, or driven from a high-performance differential amplifier such as the ad8138 illustrated in figure 9. a in a in 0.1 f 25 25 1:1 50 analog signal source ad9214 figure 8. single-ended-to-differential conversion using a transformer special care was taken in the design of the analog input section of the ad9214 to prevent damage and corruption of data when the input is overdriven. the optimal input range is 1.0 v p-p, but the ad9214 can support a 2.0 v p-p input range with some degra- dation in performance (see dfs/gain pin description a bove).
rev. d ad9214 C13C ad9214 50 analog signal source 15pf 50 50 vocm + + ad8138 500 500 500 500 0.1 f av dd 10k 5k a in a in figure 9. dc-coupled analog input circuit power supplies the ad9214 has two power supplies, av dd and drv dd . av dd and agnd supply power to all the analog circuitry, the inputs and the internal timing and digital error correction circuits. av dd supply current will vary slightly with encode rate, as noted in the typical performance characteristics section. drv dd and dgnd supply only the cmos digital outputs, allowing the user to adjust the voltage level to match down- stream logic. drv dd curr ent will vary depending on the voltage level, external loading capacitance, and the encode frequency. designs that mini- mize external load capacitance will reduce power consumption and reduce supply noise that may affect adc performance. the maximum drv dd current can be calculated as i v c fencode n drv drv load dd dd = where n is the number of output bits, 10 in the case of the ad9214. this maximum current is for the condition of every output bit switching on every clock cycle, which can only occur for a full scale square wave at the nyquist frequency, f encode /2. in practice, i drv dd will be the average number of output bits switching, which will be determined by the encode rate and the characteristics of the analog input signal. the performance curves section provides a reference of i drv dd versus encode rate for a 10.3 mhz sine wave driving the analog input. both power supply connections should be decoupled to ground at or near the package connections, using high quality, ceramic chip capacitors. a single ground plane is recommended for all ground (agnd and dgnd) connections. the pwrdn control pin configures the ad9214 for a sleep mode when it is logic high. pwrdn floats logic low for normal operation. in sleep mode, the adc is not active, and will consume less power. when switching from sleep mode to normal operation, the adc will need ~15 clock cycles to recover to valid output data. digital outputs care must be taken when designing the data receivers for the ad9214. it is recommended that the digital outputs drive a series resistor (e.g., 100 ? ) followed by a gate like the 74lcx821. to minimize capacitive loading, there should be only one gate on each output pin. an example of this is shown in the evaluation board schematic in figure 10. the series resistors should be placed as close to the ad9214 as possible to limit the amount of current that can flow into the output stage. these switching currents are confined between ground (dgnd) and the drv dd pins. standard ttl gates should be avoided since they can appreciably add to the dynamic switching currents of the ad9214. it should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. digital output timing is guaranteed with 10 pf loads. layout information the schematic of the evaluation board (figure 10) represents a typical implementation of the ad9214. a multilayer board is recommended to achieve best results. it is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. the pinout of the ad9214 facilitates ease of use in the implementation of high frequency, high resolution design practices. all of the digital outputs and their supply and ground pin connections are segre- gated to one side of the package, with the inputs on the opposite side for isolation purposes. care should be taken when routing the digital output traces. to prevent coupling through the digital outputs into the analog portion of the ad9214, minimal capacitive loading should be placed on these outputs. it is recommended that a fan-out of only one gate should be used for all ad9214 digital outputs. the layout of the encode circuit is equally critical. any noise received on this circuitry will result in corruption in the digitiza- tion process and lower overall performance. the encode clock must be isolated from the digital outputs and the analog inputs. evaluation board the ad9214 evaluation board offers designers an easy way to evaluate device performance. the user must supply an analog input signal, encode clock reference, and power supplies. the digital outputs of the ad9214 are latched on the evaluation board, and are available with a data ready signal at a 40-pin edge connector. please refer to the evaluation board schematic, layout, and bill of materials. power connections power to the board is supplied via three detachable, 4-pin power strips ( u4, u9, and u10). these 12 pins should be d riven as outlined in the table ii. table ii. power supply connections for ad9214 evaluation board external supply pin designator required 1 lvc 3 v 3 +5 v +5 v (optional z1 supply) 5 5 v 5 v (optional z1 supply) 7 vcc 3 v 9 vdd 3 v 11 dac 5 v 2, 4, 6, gnd ground 8, 10, 12 please note that the +5 v and 5 v supplies are optional, and only required if the user adds differential op amp z1 to the board.
rev. d ad9214 C14C reference circuit the evaluation board is configured at assembly to use the ad9214 s on-board reference. to supply an external reference, the user must connect the refsense pin to vcc by removing the jumper block connecting e25 to e26, and placing it between e19 and e24. in this configuration, an external 1.25 v reference must be connected to jumper connection e23. jumper connections e19 e21, e24, and resistors r13 r14 are omitted at assembly, and not used in the evaluation of the ad9214. gain/data format the evaluation board is assembled with the dfs/gain pin connected to ground; this configures the ad9214 for a 1 v p-p analog input range, and offset binary data format. the user may remove this jumper and replace it to make one of the connections described in the table below to configure the ad9214 for different gain and output data format options. table iii. data format and gain configuration for evaluation board dfs/gain jumper dfs/gain differential output data placement connection a in range format e18 to e12 agnd 1 v p-p offset binary e16 to e11 av dd 1 v p-p two s complement e15 to e14 ref 2 v p-p two s complement e17 to e13 floating 2 v p-p offset binary power-down the evaluation board is configured at assembly so that the pwrdn input floats low for normal operating condition. the user may add a jumper between option holes e5 and e6 to connect pwrdn to avcc, configuring the ad9214 for power- down mode. encode signal and distribution the encode input signal should drive smb connector j5, which has an on-board 50 ? termination. a standard cmos compatible pulse source is recommended. alternatively, the user can adjust the dc level of an ac-coupled clock source by adding resistor r11, normally omitted. j5 drives the ad9214 encode input and one gate of u12, which buffers and distributes the clock signal to the on-board latch (u3), the reconstruction dac (u11), and the output data connector (u2). the board comes assem bled with timing options optimized for the dac and latch; the user may invert the dr signal at pin 37 of edge connector u2 by removing the jumper block between e34 and e35, and reinstalling it between e35 and e36. analog input the analog input signal is connected to the evaluation board by smb connector j1. as configured at assembly, the signal is ac coupled by capacitor c10 to transformer t1. this 1:1 transformer provides a 50 ? termination for connector j1 via 25 ? resistors r1 and r4. t1 also converts the signal at j1 into a differential signal for the analog inputs of the ad9214. resistor r3, normally omitted, can be used to terminate j1 if the transformer is removed. the user can reconfigure the board to drive the ad9214 single- endedly by removing the jumper block between e1 and e3, and replacing it between e3 and e2. in this configuration, capacitor c2 stabilizes the self-bias of a in , and resistor r2 provides a matched impedance for a 50 ? source at j1. transformer t1 can be bypassed by moving the jumper normally between e40 and e38 to connect e40 to e37, and moving the jumper normally between e39 and e10 to connect e7 to e10. in this configuration, the analog input of the ad9214 is driven single ended, directly from j1; and r3 (normally omitted) should be installed to terminate any cable connected to j1. using the ad8138 an optional driver circuit for the analog input, based on the ad8138 differential amplifier, is included in the layout of the ad9214 evaluation board. this portion of the evaluation circuit is not populated when the board is manufactured, but can be easily be added by the user. resistors r5, r16, r18, and r25 are the feedback network that sets the gain of the ad8138. resistors r23 and r24 set the common-mode voltage at the output of the op amp. resistors r27 and r28, and capacitor c15, form a low-pass filter at the output of the ad8138, limiting its noise contribution into the ad9214. once the drive circuit is populated, the user should remove the jumper block normally between e40 and e38, and place it between e40 and e41. this will ac-couple the analog input signal from smb connector j1 to the ad8138 drive circuit. the user will also need to remove the jumper blocks that normally connect e39 to e10 and e1 to e3 to remove transformer t1 from the circuit. dac reconstruction circuit the data available at output connector u2 is also reconstructed by dac u11, the ad9752. this 12-bit, high-speed digital-to-analog converter is included as a tool in setting up and debugging the evaluation board. it should not be used to measure the per- formance of the ad9214, as its performance will not accurately reflect the performance of the adc. the dac s output, available at j2, will drive 50 ? . the user can add a jumper block between e8 and e9 to activate the sleep function of the dac.
rev. d ad9214 C15C ad9214/pcb bill of material # quantity reference designator device package value 1 1 n/a pcb 219 c1 c3, c5 c14, c16 c20, c25 c28 capacitor 603 0.1 f 3 4 c21 c24 capacitor captajd 10 f 4 1 c4 capacitor 603 0.01 f 5 4 r1, r2, r4, r8 resistor 1206 25 ? 6 4 r7, r10, r12, r17 resistor 1206 50 ? 74 u5 u8 resistor rpak_742 100 ? 8 1 r21 resistor 1206 0 ? 9 2 r6, r9 resistor 1206 2000 ? 10 37 e1 e6, e8 e9, e11 e27, e29, e31 e41 test points tsw-120-07-g-s jumper connections smt-100-bk-g 11 3 j1, j2, j5 connector smb 51-52-220 12 1 u12 clock chip soic sn74lvc86 13 1 u11 dac soic ad9752 14 1 u3 latch soic 74lcx821 15 1 u1 adc/dut soic ad9214 16 1 u2 40-pin header samtec tsw-120-07-g-d 17 1 t1 transformer mini circuits adt1-1wt 18 3 u4, u9, u10 power strip newark 95f5966 power connector 25.602.5453.0 the following items are included in the pcb design, but are omitted at assembly. 19 3 c1, c20, c28 capacitor 603 0.1 f 20 2 c30, c29 capacitor captajd 10 f 21 1 c15 capacitor 603 15 pf 22 4 r5, r18, r25, r26 resistor 1206 500 ? 23 1 r23 resistor 1206 1 k ? 24 1 r24 resistor 1206 4 k ? 25 3 r11, r15, r16 resistor 1206 user select 26 2 r13, r14 resistor 1206 n/a 27 3 r27, r28, r3 resistor 1206 50 ? 28 1 r19 resistor 1206 0 ? 29 1 z1 op amp soic ad8138
rev. d ad9214 C16C 34 32 30 28 26 24 c3 0.1 f c7 0.1 f v cc v cc gnd gnd amp amp e3 e1 e2 c2 0.1 f gnd c8 0.1 f enc e4 e5 e6 gnd v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd c9 0.1 f v dd gnd v dd gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 apak_742 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 apak_742 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v dd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 apak_742 u7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c19 0.1 f clklat d9 msb d8 d7 d6 d5 e30 dtr lvc 3v gnd +5v gnd 1234 5v gnd v cc 3v gnd 1234 v dd 3v gnd dac gnd 1234 u9 u4 u10 c30 10 f c29 10 f c21 10 f c22 10 f c23 10 f c24 10 f 5v +5v lvc v cc v dd dac gnd gnd v dd clklat r16 50 r15 50 optional gnd e14 e15 v cc e11 e16 e12 e18 e13 e17 c17 0.1 f c26 0.1 f gnd gnd gnd e23 e22 v cc e24 e19 e26 e25 e20 e21 gnd gnd c25 0.1 f r13 2k r14 2k optional gnd c27 0.1 f e39 e7 e10 r4 25 r1 25 c4 0.1 f c6 0.1 f gnd gnd 1 5 3 6 2 4 gnd e37 e40 e38 c10 0.1 f e29 r3 50 optional c18 0.1 f gnd gnd r2 25 0.1 f c8 or dfs/gain refsense ref agnd1 av dd av dd agnd a in a in agnd av dd clk pwrdn d9 msb d8 d7 d6 drv dd dgnd d5 d4 d3 d2 d1 d0 lsb drv dd 1 dgnd1 ad9214a u1 u7 u8 de d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gnd v cc d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clk 74lcxb21 u3 apak_742 u8 t1 r12 50 j5 lvc r11 50 enc r21 0 r19 0 1 2 3 4 5 6 7 gnd gnd 1a 1b 1y 2a 2b 2y gnd 5n74lvc86 u12 r17 50 dr e35 e34 gnd e36 lvc enc optional 14 13 12 11 10 9 8 v cc 4b 4a 4y 3b 3a 3y clkdac e33 e31 gnd e32 lvc clklat lvc e27 e28 gnd r10 50 lvc gnd c16 0.1 f j1 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d9 msb d8 d7 d6 d5 d4 d3 d2 d1 d0 lsb gnd gnd gnd clkdac gnd gnd 1 2 3 4 5 6 7 8 9 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 nc1 nc2 clk dvdd dcom nc3 avdd icomp iouta ioutb acom nc4 fsadj refio reflo sleep ad9752 u11 e9 e8 r6 2k gnd dac gnd c12 0.1 f r9 2k gnd r8 25 gnd r7 50 gnd j2 gnd c11 0.1 f gnd c13 0.1 f dac gnd c14 0.1 f dac gnd 39 37 35 33 31 29 27 25 23 21 19 17 gnd dr gnd 13 11 9 7 5 3 1 15 40 38 36 22 20 18 16 14 12 10 8 6 4 2 gnd 37 35 33 31 29 27 25 23 21 19 17 39 13 11 9 7 5 3 1 15 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 4qpha u2 d4 d3 d2 d1 d0 optional r26 500 6 5 4 3 c20 0.1 f 5v ad8138 r25 500 vcom 1 2 8 r25 4k r23 1k 5v c1 0.1 f r5 500 r18 500 e41 c28 0.1 f v v r28 50 r27 50 c15 15pf amp amp z1 5v gnd v cc optional figure 10. pcb schematic
rev. d ad9214 C17C figure 11. pcb top side silkscreen \ figure 12. pcb top side copper figure 13. pcb bottom side silkscreen figure 14. pcb bottom side copper figure 15. pcb ground layerlayer tbd figure 16. pcb power layerslayers 3 and 4
rev. d ad9214 C18C outline dimensions dimensions shown in inches and (mm). 28-lead shrink small outline package (rs-28) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) seating plane 0.0256 (0.65) bsc 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 15 14 1 0.407 (10.34) 0.397 (10.08) pin 1 controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design
rev. d ad9214 C19C revision history location page data sheet changed from rev. c to rev. d. edit to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 tpc 15 replaced with new figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 edit to figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 07/01?ata sheet changed from rev. b to rev. c. edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 05/01?ata sheet changed from rev. a to rev. b. changes to psrr specifications in ad9214-65, ad9214-80, ad9214-105 columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 change to snr specifications in ad9214-105 column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to third harmonic distortion specifications in ad9214-105 column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 01/01?ata sheet changed from rev. 0 to rev. a. changes to dc specifications in ad9214-65, ad9214-80, ad9214-105 columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to ac specifications in ad9214-65, ad9214-105 columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
C20C c01693C0C2/02(d) printed in u.s.a.

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